The present invention relates to the art of high speed logic circuits, including the design of fast delay locked loops and phase locked loops. In particular, the invention relates to circuit techniques for fast logic or inversion stages in delay locked loops, phase locked loops, and carry chains.
Internal multiphase clocks are common in modern high-speed integrated circuits; they are particularly handy in the design of memory elements of complex logic circuits. It is also common that multiphase clocks operate at frequencies that are a multiple of an input reference clock frequency.
On-chip phase locked loops are commonly used to generate high-speed internal clocks that operate at a multiple of a reference frequency. On-chip delay locked loops may be used to subdivide such high speed clocks into the desired multiphase clocks.
Commonly an on-chip delay-locked loop has a voltage-variable delay line having one or more voltage-variable delay stages. Multiphase outputs are often tapped from various points, separated by one or more of the voltage-variable delay stages, along the delay line. Typically, a delayed output from the voltage variable delay line is compared with a repetitive reference signal to generate a feedback voltage that adjusts the delay of the voltage-variable delay stages to lock that delayed output relative to the reference.
CMOS voltage-variable delay stages typically incorporate a pullup transistor and at least one pulldown transistor; there may also be a stage load capacitor in addition to the parasitic load capacitance of the devices and the input of the following stage. At least one, and occasionally both, of these transistors is controlledxe2x80x94it may be in series with an additional device that limits current through the pullup or pulldown transistor to a voltage-controlled value. Alternatively, the voltage swing of a gate of the pullup or pulldown transistor may be limited such that the current through the device is held to a controlled value.
For high-speed operation of a delay locked loop with narrow time differences between multiphase outputs, it is desirable that the delay of each stage be low. For example, if output phases A and B are to differ by N time when locked to a reference F, then it is desirable that N be an integer multiple of the voltage-variable stage delay S as trimmed by the feedback signal. If F is one GHz, with A and B separated in phase by 45 degrees, S should be an integer fraction of 125 picoseconds. Stage delays less than and equal to this magnitude are difficult to attain in prior-art voltage-variable delay stages.
It is also known that a voltage-controlled oscillator for use in a phase-locked loop may be built of voltage-variable delay stages connected in ring-oscillator configuration. Ring-oscillators of this type normally have an odd number of inverting delay stages, coupled in a loop where the last stage of the chain feeds the input to the chain. Alternatively, they may have an even number of inverting, or any number of noninverting, delay stages coupled with an inverter or inverting gate between the output of the delay chain and the input of the delay chain. Such oscillators often have provisions made for initialization of the delay chain.
A voltage-variable delay line suitable for use in high-speed delay-locked loops and ring oscillators of phase-locked loops has multiple voltage-variable delay stages. The voltage-variable delay stages use a feedforward path to ratioed pullup and pulldown devices, in parallel with pullup and pulldown devices of the delay stage, to provide faster and more consistent minimum propagation delays than achieved with voltage-variable delay stages of conventional design.
With feedforward devices as per the invention, the voltage-variable delay stages can be thought of as operating in a voltage-variable speedup mode, as opposed to the usual voltage-variable slowdown mode.
Feedforward devices similar to those of the voltage-variable delay stages have also been found useful for high speed logic gates, including ripple-carry chains.